1. Field of the Invention
The present invention generally relates to a method for fabricating a gate electrode on a substrate, and more particularly to a method for reducing the dielectric constant of gate electrode.
2. Description of the Prior Art
The use of conventional gate electrode and gate dielectric material is becoming increasingly problematic as feature sizes of semiconductor devices are continuing to be scaled to smaller dimensions. Among the problems encountered include increased resistance of the gate electrode, leakage of the gate dielectric, and polysilicon gate depletion effects. In an effort to overcome these problems, alternative materials are being investigated to replace conventional gate dielectric and gate electrode materials.
Refractory metals or refractory metal alloys, their nitrides, and aluminum are alternative materials currently being investigated for use as gate electrodes. These materials offer potential advantages over materials such as polysilicon because of their patternability, low sheet resistance, and scalability to advanced metal oxide semiconductor technologies. Among the refractory metals currently being considered include titanium, tantalum, tungsten, molybdenum, zirconium, or the like.
In selecting refractory metal materials for use as a gate electrode, a number of factors must be considered. Among these include the electric, chemical, and physical properties of the refractory metal material. The selection process is further complicated because these properties can change as the refractory metal material is subjected to various thermal processing steps. Failure to compensate for these thermally induced changes can impact yield and potentially affect the reliability of the semiconductor device.
In generally, after the isolation structure such as STI (shallow trench isolation) or LOCOS (local oxidation) formed in the substrate, the SiO2 or SiN as a gate dielectric material is formed on the substrate. In order to increase the S/D current (source/drain current), therefore, the thickness of gate dielectric must be reduced. However the SiO2 or SiN, has EOT (effective oxide thickness) is smaller than 17 angstrom such that the tunneling will be occurred, and further the gate leakage current will be increased extremely.
Further another disadvantage is that the dielectric material such as Hf (hafnium), Zr (zirconium), La2O3 (lanthanum oxide), Y2O3 (yttrium oxide), and Al-doped Zr-silicate ((Al2O3)(ZrO2)x(SiO2)1-x-y are deposited on the semiconductor device during the CMOS (complementary metal oxide semiconductor) process. The dielectric material has been attention for low resistivity, and the thermal and chemical stability are poor such as for Hf and Zr. Furthermore, other dielectric materials are used only for 100 nm CMOS (complementary metal oxide semiconductor) fabrication such as Ta2O5 (tantalum pentoxide) and PZT (Lead Zirconium Titanate).